DMA

This section introduces the Direct Memory Access (DMA) APIs including terms and acronyms, supported features, software architecture, details on how to use this driver, enums, structures and functions. More...

Overview

This section introduces the Direct Memory Access (DMA) APIs including terms and acronyms, supported features, software architecture, details on how to use this driver, enums, structures and functions.

Terms and Acronyms

Terms	Details
DMA	Direct Memory Access.
FIFO	First in, First Out.
VFF DMA	Virtual FIFO DMA.

Supported Features

This controller supports DMA devices, which have multiple hardware DMA channels. Different channels can transfer data simultaneously.
There are three DMA channel types: FULL-SIZE DMA, HALF-SIZE DMA and Virtual FIFO DMA. FULL-SIZE DMA supports data transfer from
memory to memory. HALF-SIZE DMA supports data transfer from peripheral to memory or opposite direction. Virtual FIFO DMA also supports
data transfer between memory and peripheral, but it has an additional FIFO control engine on memory side; the memory space will be FIFO.
For more details, please refer to the DMA datasheet.

Note

• DMA Interrupt Description:
  There are four kinds of interrupt notifications in various DMA channels.
  The interrupt of transfer completion notifies event of the completion of transfer for both FULL-SIZE DMA and HALF-SIZE DMA.
  The interrupt of half transfer completion notifies event that half of tranfser data has been completed and it is ony for HALF-SIZE DMA.
  VFF DMA (Virtual FIFO DMA) has two kinds of interrupt, and one notifies event that FIFO data is over or under a certain threshold,
  the other is FIFO timeout interrupt which shows there is no new data into the FIFO in the previous FIFO timeout bus cycles.
  
  • VFF DMA FIFO data interrupt:
    • For data transfer from peripheral to memory, interrupt is issued when data in FIFO are more than or equal to threshod;
    • For data transfer from memory to peripheral, interrupt is issued when data in FIFO are less than threshod;
• The Source and Destination Configuration of Data Transfer:
  • For FULL-SIZE DMA, the src_addr and dst_addr register specify the base address of transfer source and destination respectively for a DMA channel.
    Data transfer is from src_addr to dst_addr. The src_addr and dst_addr are both memory space.
  • For HALF-SIZE DMA and VFF DMA, fix_addr register specifies the peripheral side and prog_addr register specifies the memory side.
    If transfer direction is from peripheral to memory, fix_addr is source and prog_addr is destination. If transfer direction is opposite,
    fix_addr is destination and prog_addr is source.
  • For VFF DMA, the prog_addr register is FIFO base address and the FIFO engine uses HWPTR and SWPTR to control FIFO access:
    • For data transfer from peripheral to memory, HWPTR is write pointer and SWPTR is read pointer;
    • For data transfer from memory to peripheral, HWPTR is read pointer and SWPTR is write pointer;
      
    • HWPTR and SWPTR are offset of FIFO base address.

How to Use This Driver

• SW Architecture:
  See Overview of M-HAL SW Architecture for details of the SW architecture.

  This section describes the Common Interface API definition and provides an example on freeRTOS to show how to use these APIs to develop an OS-related DMA driver.
  

• The OS-HAL FreeRTOS Driver Sample Code as Following.
  freeRTos DMA sample code on github

Modules
	Define
	This section introduces the Macro definition which is used as DMA M-HAL's API error return type.
	Enum
	This section describes the enumeration definition in DMA device driver.
	Function
	This section provides DMA M-HAL APIs(defined as Common Interface) to fully control the MediaTek DMA HW.
	Struct
	This section introduces the structure definition in DMA M-HAL.
	Typedef
	This section introduces the typedef used by DMA M-HAL.