mhal_dma.h

/*
 * (C) 2005-2020 MediaTek Inc. All rights reserved.
 *
 * Copyright Statement:
 *
 * This MT3620 driver software/firmware and related documentation
 * ("MediaTek Software") are protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. ("MediaTek"). You may only use, reproduce, modify, or
 * distribute (as applicable) MediaTek Software if you have agreed to and been
 * bound by this Statement and the applicable license agreement with MediaTek
 * ("License Agreement") and been granted explicit permission to do so within
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 * please cease any access or use of MediaTek Software immediately.
 *
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 */

#ifndef __MHAL_DMA_H__
#define __MHAL_DMA_H__

#include "mhal_osai.h"

#define DMA_EPTR 1

#define DMA_EPARAM 2

#define DMA_EBUSY 3

enum dma_dir {
    MEM_2_PERI = 0,
    PERI_2_MEM = 1
};

enum dma_type {
    DMA_TYPE_FULLSIZE = 0,
    DMA_TYPE_HALFSIZE = 1,
    DMA_TYPE_VFF = 2,
};

enum dma_param {
    DMA_PARAM_RLCT = 0,
    DMA_PARAM_FIX_ADDR = 1,
    DMX_PARAM_PROG_ADDR = 2,
    DMA_PARAM_VFF_FIFO_SIZE = 3,
    DMA_PARAM_VFF_FIFO_CNT = 4,
    DMA_PARAM_VFF_HWPTR = 5,
    DMA_PARAM_VFF_SWPTR = 6,
};

enum dma_status {
    DMA_STATUS_INTERRUPT = 1U << 0,
    DMA_STATUS_RUNNING = 1U << 1,
    DMA_STATUS_PAUSE = 1U << 2,
};

enum dma_transize {
    DMA_SIZE_BYTE = 0,
    DMA_SIZE_SHORT,
    DMA_SIZE_LONG,
};

enum dma_burst_type {
    DMA_BURST_TYPE_SINGLE = 0x0,
    DMA_BURST_TYPE_4BEAT = 0x2,
    DMA_BURST_TYPE_8BEAT = 0x4,
    DMA_BURST_TYPE_16BEAT = 0x6
};

typedef void (*dma_isr_callback)(void *user_data);

struct dma_ctrl {
    enum dma_dir dir;
    u8 wrap_en;
    u8 wrap_side;
    u8 int_en;
    u8 timeout_int_en;
    u8 half_int_en;
    enum dma_burst_type burst_type;
    u8 bw_transfer_en;
    u8 dreq;
    u8 dst_inc_en;
    u8 src_inc_en;
    enum dma_transize transize;
};

struct dma_config {
    u32 addr_1;
    u32 addr_2;
    u32 wrap_point;
    u32 wrap_to_addr;
    u8 reload_en;
    u32 count;
    u8 bw_limiter;
    u8 alert_cmp_type;
    u32 alert_len;
    u32 fifo_size;
    u32 timeout_cnt;
    dma_isr_callback isr_callback_1;
    dma_isr_callback isr_callback_2;
    void *isr_cb_data_1;
    void *isr_cb_data_2;
};

struct dma_controller {
    void __iomem *base;;
    u8 chn;
    enum dma_type chn_type;
    struct dma_ctrl *ctrls;
    struct dma_config *cfg;
};

#ifdef __cplusplus
extern "C" {
#endif

int mtk_mhal_dma_config(struct dma_controller *controller);

int mtk_mhal_dma_start(struct dma_controller *controller);

int mtk_mhal_dma_stop(struct dma_controller *controller);

int mtk_mhal_dma_pause(struct dma_controller *controller);

int mtk_mhal_dma_resume(struct dma_controller *controller);

int mtk_mhal_dma_get_status(struct dma_controller *controller);

int mtk_mhal_dma_set_param(struct dma_controller *controller,
               enum dma_param param, u32 value);

int mtk_mhal_dma_get_param(struct dma_controller *controller,
               enum dma_param param);

int mtk_mhal_dma_clear_irq_status(struct dma_controller *controller);

int mtk_mhal_dma_dump_reg(struct dma_controller *controller);

int mtk_mhal_dma_clock_enable(struct dma_controller *controller);

int mtk_mhal_dma_clock_disable(struct dma_controller *controller);

int mtk_mhal_dma_reset(struct dma_controller *controller);

int mtk_mhal_dma_update_swptr(struct dma_controller *controller,
                    u32 length_byte);

int mtk_mhal_dma_vff_read_data(struct dma_controller *controller,
                    u8 *buffer, u32 length);

int mtk_mhal_dma_clr_dreq(struct dma_controller *controller);

#ifdef __cplusplus
}
#endif

#endif