mhal_gpio.h

/*
 * (C) 2005-2020 MediaTek Inc. All rights reserved.
 *
 * Copyright Statement:
 *
 * This MT3620 driver software/firmware and related documentation
 * ("MediaTek Software") are protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. ("MediaTek"). You may only use, reproduce, modify, or
 * distribute (as applicable) MediaTek Software if you have agreed to and been
 * bound by this Statement and the applicable license agreement with MediaTek
 * ("License Agreement") and been granted explicit permission to do so within
 * the License Agreement ("Permitted User"). If you are not a Permitted User,
 * please cease any access or use of MediaTek Software immediately.
 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
 * PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS
 * ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
 * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
 * INCORPORATED IN, OR SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO
 * LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
 * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
 * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
 * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
 * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
 * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED
 * HEREUNDER WILL BE ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
 * RECEIVER TO MEDIATEK DURING THE PRECEDING TWELVE (12) MONTHS FOR SUCH
 * MEDIATEK SOFTWARE AT ISSUE.
 */

#ifndef __MHAL_GPIO_H__
#define __MHAL_GPIO_H__
#include "mhal_osai.h"

#define EINVAL  1

#define EPIN        2

#define EINVALFUNC      3

#define EFREE       4

#define EQUEST      5

#define ERROR       6

typedef enum {
    MHAL_GPIO_0 = 0,
    MHAL_GPIO_1 = 1,
    MHAL_GPIO_2 = 2,
    MHAL_GPIO_3 = 3,
    MHAL_GPIO_4 = 4,
    MHAL_GPIO_5 = 5,
    MHAL_GPIO_6 = 6,
    MHAL_GPIO_7 = 7,
    MHAL_GPIO_8 = 8,
    MHAL_GPIO_9 = 9,
    MHAL_GPIO_10 = 10,
    MHAL_GPIO_11 = 11,
    MHAL_GPIO_12 = 12,
    MHAL_GPIO_13 = 13,
    MHAL_GPIO_14 = 14,
    MHAL_GPIO_15 = 15,
    MHAL_GPIO_16 = 16,
    MHAL_GPIO_17 = 17,
    MHAL_GPIO_18 = 18,
    MHAL_GPIO_19 = 19,
    MHAL_GPIO_20 = 20,
    MHAL_GPIO_21 = 21,
    MHAL_GPIO_22 = 22,
    MHAL_GPIO_23 = 23,
    MHAL_GPIO_24 = 24,
    MHAL_GPIO_25 = 25,
    MHAL_GPIO_26 = 26,
    MHAL_GPIO_27 = 27,
    MHAL_GPIO_28 = 28,
    MHAL_GPIO_29 = 29,
    MHAL_GPIO_30 = 30,
    MHAL_GPIO_31 = 31,
    MHAL_GPIO_32 = 32,
    MHAL_GPIO_33 = 33,
    MHAL_GPIO_34 = 34,
    MHAL_GPIO_35 = 35,
    MHAL_GPIO_36 = 36,
    MHAL_GPIO_37 = 37,
    MHAL_GPIO_38 = 38,
    MHAL_GPIO_39 = 39,
    MHAL_GPIO_40 = 40,
    MHAL_GPIO_41 = 41,
    MHAL_GPIO_42 = 42,
    MHAL_GPIO_43 = 43,
    MHAL_GPIO_44 = 44,
    MHAL_GPIO_45 = 45,
    MHAL_GPIO_46 = 46,
    MHAL_GPIO_47 = 47,
    MHAL_GPIO_48 = 48,
    MHAL_GPIO_49 = 49,
    MHAL_GPIO_50 = 50,
    MHAL_GPIO_51 = 51,
    MHAL_GPIO_52 = 52,
    MHAL_GPIO_53 = 53,
    MHAL_GPIO_54 = 54,
    MHAL_GPIO_55 = 55,
    MHAL_GPIO_56 = 56,
    MHAL_GPIO_57 = 57,
    MHAL_GPIO_58 = 58,
    MHAL_GPIO_59 = 59,
    MHAL_GPIO_60 = 60,
    MHAL_GPIO_61 = 61,
    MHAL_GPIO_62 = 62,
    MHAL_GPIO_63 = 63,
    MHAL_GPIO_64 = 64,
    MHAL_GPIO_65 = 65,
    MHAL_GPIO_66 = 66,
    MHAL_GPIO_67 = 67,
    MHAL_GPIO_68 = 68,
    MHAL_GPIO_69 = 69,
    MHAL_GPIO_70 = 70,
    MHAL_GPIO_71 = 71,
    MHAL_GPIO_72 = 72,
    MHAL_GPIO_73 = 73,
    MHAL_GPIO_74 = 74,
    MHAL_GPIO_75 = 75,
    MHAL_GPIO_76 = 76,
    MHAL_GPIO_77 = 77,
    MHAL_GPIO_78 = 78,
    MHAL_GPIO_79 = 79,
    MHAL_GPIO_80 = 80,
    MHAL_GPIO_81 = 81,
    MHAL_GPIO_82 = 82,
    MHAL_GPIO_83 = 83,
    MHAL_GPIO_84 = 84,
    MHAL_GPIO_85 = 85,
    MHAL_GPIO_86 = 86,
    MHAL_GPIO_87 = 87,
    MHAL_GPIO_88 = 88,
    MHAL_GPIO_89 = 89,
    MHAL_GPIO_90 = 90,
    MHAL_GPIO_91 = 91,
    MHAL_GPIO_92 = 92,
    MHAL_GPIO_93 = 93,
    MHAL_GPIO_MAX
} mhal_gpio_pin;

typedef enum {
    MHAL_GPIO_MODE_0 = 0,
    MHAL_GPIO_MODE_1 = 1,
    MHAL_GPIO_MODE_2 = 2,
    MHAL_GPIO_MODE_3 = 3,
    MHAL_GPIO_MODE_4 = 4,
    MHAL_GPIO_MODE_5 = 5,
    MHAL_GPIO_MODE_6 = 6,
    MHAL_GPIO_MODE_7 = 7,
    MHAL_GPIO_MODE_MAX
} mhal_gpio_mode;

typedef enum {
    MHAL_GPIO_DIRECTION_INPUT  = 0,
    MHAL_GPIO_DIRECTION_OUTPUT = 1
} mhal_gpio_direction;


typedef enum {
    MHAL_GPIO_DATA_LOW  = 0,
    MHAL_GPIO_DATA_HIGH = 1
} mhal_gpio_data;

typedef enum {
    MHAL_CM4_GPIO_PWM_GRP0_BASE = 0,
    MHAL_CM4_GPIO_PWM_GRP1_BASE = 1,
    MHAL_CM4_GPIO_PWM_GRP2_BASE = 2,
    MHAL_CM4_GPIO_PWM_GRP3_BASE = 3,
    MHAL_CM4_GPIO_PWM_GRP4_BASE = 4,
    MHAL_CM4_GPIO_PWM_GRP5_BASE = 5,
    MHAL_CM4_ISU0_I2C_BASE = 6,
    MHAL_CM4_ISU1_I2C_BASE = 7,
    MHAL_CM4_ISU2_I2C_BASE = 8,
    MHAL_CM4_ISU3_I2C_BASE = 9,
    MHAL_CM4_ISU4_I2C_BASE = 10,
    MHAL_CM4_ADC_BASE = 11,
    MHAL_CA7_GPIO_BASE = 12,
    MHAL_CM4_I2S0_BASE = 13,
    MHAL_CM4_I2S1_BASE = 14,
    MHAL_PINMUX_BASE = 15,
    MHAL_GPIO_REG_BASE_MAX
} mhal_gpio_reg_base;


struct mtk_pinctrl_desc_pin {
    bool pinctrl_free;
};

struct mtk_pinctrl_controller {
    void __iomem *base[MHAL_GPIO_REG_BASE_MAX];
    unsigned int  gpio_mode_bits;
    unsigned int  max_gpio_mode_per_reg;
    unsigned char  port_shf;
    unsigned char  port_mask;
    unsigned int pinmux_offset;
};

#ifdef __cplusplus
extern "C" {
#endif

int mtk_mhal_gpio_get_input(struct mtk_pinctrl_controller *pctl,
    u32 pin, mhal_gpio_data *pvalue);

int mtk_mhal_gpio_set_output(struct mtk_pinctrl_controller *pctl,
    u32 pin, u32 out_val);

int mtk_mhal_gpio_get_output(struct mtk_pinctrl_controller *pctl,
    u32 pin, mhal_gpio_data *pvalue);

int mtk_mhal_gpio_set_direction(
    struct mtk_pinctrl_controller *pctl, u32 pin, u32 dir);

int mtk_mhal_gpio_get_direction(struct mtk_pinctrl_controller *pctl,
    u32 pin, mhal_gpio_direction *pvalue);

int mtk_mhal_gpio_set_pullen_pullsel(
    struct mtk_pinctrl_controller *pctl, u32 pin, bool enable, bool isup);

int mtk_mhal_gpio_pmx_set_mode(
    struct mtk_pinctrl_controller *pctl, u32 pin, u32 mode);

int mtk_mhal_gpio_pmx_get_mode(struct mtk_pinctrl_controller *pctl,
    u32 pin, u32 *pvalue);

#ifdef __cplusplus
}
#endif

#endif