mhal_gpioif.h

/*
 * (C) 2005-2020 MediaTek Inc. All rights reserved.
 *
 * Copyright Statement:
 *
 * This MT3620 driver software/firmware and related documentation
 * ("MediaTek Software") are protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. ("MediaTek"). You may only use, reproduce, modify, or
 * distribute (as applicable) MediaTek Software if you have agreed to and been
 * bound by this Statement and the applicable license agreement with MediaTek
 * ("License Agreement") and been granted explicit permission to do so within
 * the License Agreement ("Permitted User"). If you are not a Permitted User,
 * please cease any access or use of MediaTek Software immediately.
 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
 * PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS
 * ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
 * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
 * INCORPORATED IN, OR SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO
 * LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
 * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
 * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
 * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
 * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
 * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED
 * HEREUNDER WILL BE ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
 * RECEIVER TO MEDIATEK DURING THE PRECEDING TWELVE (12) MONTHS FOR SUCH
 * MEDIATEK SOFTWARE AT ISSUE.
 */

#ifndef __MHAL_GPIOIF_H__
#define __MHAL_GPIOIF_H__
#include "mhal_osai.h"

#define GPIOIF_EINVAL   1

#define GPIOIF_EPTR     2

#define MAX_FIFO_ENTRY_CNT  16

#define MAX_CTRL_SETTING    6

#define MAX_MIN_PURSE_WIDTH 0x3fff

#define IRQ_GPIOIF_EVENT_C_R_LOW        (0)

#define IRQ_GPIOIF_EVENT_C_R_HIGH       (1)

#define IRQ_GPIOIF_RESET_DONE           (2)

#define IRQ_GPIOIF_EVENT_C_OVERFLOW     (8)

#define IRQ_GPIOIF_EVENT_C_UNDERFLOW    (9)

#define IRQ_GPIOIF_W_CFIFO0_WHEN_FULL   (12)

#define IRQ_GPIOIF_W_CFIFO1_WHEN_FULL   (13)

#define IRQ_GPIOIF_W_GPIO_2_RESET_CFIFO0_WHEN_FULL  (14)

#define IRQ_GPIOIF_W_GPIO_2_RESET_CFIFO1_WHEN_FULL  (15)

#define IRQ_GPIOIF_CFIFO0_NOT_EMPTY     (16)

#define IRQ_GPIOIF_CFIFO1_NOT_EMPTY     (17)

#define IRQ_GPIOIF_R_CFIFO0_WHENEMPTY   (24)

#define IRQ_GPIOIF_R_CFIFO1_WHENEMPTY   (25)

#define IRQ_GPIOIF_ALL_ENABLE   (1 << IRQ_GPIOIF_EVENT_C_R_LOW) |\
    (1 << IRQ_GPIOIF_EVENT_C_R_HIGH) |\
    (1 << IRQ_GPIOIF_RESET_DONE) |\
    (1 << IRQ_GPIOIF_EVENT_C_OVERFLOW) |\
    (1 << IRQ_GPIOIF_EVENT_C_UNDERFLOW) |\
    (1 << IRQ_GPIOIF_W_CFIFO0_WHEN_FULL) |\
    (1 << IRQ_GPIOIF_W_CFIFO1_WHEN_FULL) |\
    (1 << IRQ_GPIOIF_W_GPIO_2_RESET_CFIFO0_WHEN_FULL) |\
    (1 << IRQ_GPIOIF_W_GPIO_2_RESET_CFIFO1_WHEN_FULL) |\
    (1 << IRQ_GPIOIF_CFIFO0_NOT_EMPTY) |\
    (1 << IRQ_GPIOIF_CFIFO1_NOT_EMPTY) |\
    (1 << IRQ_GPIOIF_R_CFIFO0_WHENEMPTY) |\
    (1 << IRQ_GPIOIF_R_CFIFO1_WHENEMPTY)

typedef enum {
    MHAL_GPIOIF_CLOCK_26MHZ = 0,
    MHAL_GPIOIF_CLOCK_32KHZ = 1,
    MHAL_GPIOIF_CLOCK_125MHZ = 2,
    MHAL_GPIOIF_CLOCK_200MHZ = 3,
    MHAL_GPIOIF_CLOCK_MAX
} mhal_gpioif_source_clock;

typedef enum {
    MHAL_GPIOIF_GROUP_0 = 0,
    MHAL_GPIOIF_GROUP_1 = 1,
    MHAL_GPIOIF_GROUP_2 = 2,
    MHAL_GPIOIF_GROUP_3 = 3,
    MHAL_GPIOIF_GROUP_4 = 4,
    MHAL_GPIOIF_GROUP_5 = 5,
    MHAL_GPIOIF_GROUP_MAX
} mhal_gpioif_group;

typedef enum {
    MHAL_GPIOIF_DIRECTION_MODE = 0,
    MHAL_GPIOIF_UP_DOWN_MODE = 1,
    MHAL_GPIOIF_QUA_MODE = 2,
    MHAL_GPIOIF_EVNET_COUNTER_MODE_MAX
} mhal_gpioif_event_counter_mode;

typedef enum {
    MHAL_GPIOIF_EVENT_COUNTER_MODE = 0,
    MHAL_GPIOIF_CAP_COUNTER_MODE = 1,
    MHAL_GPIOIF_EVENT_CAP_COUNTER_MODE = 2,
    MHAL_GPIOIF_MODE_MAX
} mhal_gpioif_mode;

typedef enum {
    MHAL_GPIOIF_NOT_SA_LIMIT_V = 0,
    MHAL_GPIOIF_SA_LOW_LIMIT_V = 1,
    MHAL_GPIOIF_SA_HIGH_LIMIT_V = 2,
    MHAL_GPIOIF_SA_RESET_LOW_LIMIT_V = 3,
    MHAL_GPIOIF_SA_RESET_HIGH_LIMIT_V = 4,
    MHAL_GPIOIF_SA_MAX
} mhal_gpioif_sa_mode_limit_select;


typedef enum {
    MHAL_GPIOIF_NOT_INTERRUPT = 0,
    MHAL_GPIOIF_INTERRUPT_LOW_LIMIT_V = 1,
    MHAL_GPIOIF_INTERRUPT_HIGH_LIMIT_V = 2,
    MHAL_GPIOIF_INTERRUPT_BOTH_V = 3,
    MHAL_GPIOIF_INTERRUPT_MAX
} mhal_gpioif_interrupt_limit_select;

typedef enum {
    MHAL_GPIOIF_GPIO_0_RISING = 0,
    MHAL_GPIOIF_GPIO_0_FALLING = 1,
    MHAL_GPIOIF_GPIO_0_BOTH_RISING_FALLING = 2,
    MHAL_GPIOIF_GPIO_0_RISING_RESERVED = 3,
    MHAL_GPIOIF_GPIO_0_EDGE_TYPE_MAX
} mhal_gpioif_gpio_0_edge_type;

typedef enum {
    MHAL_GPIOIF_GPIO_1_RISING = 0,
    MHAL_GPIOIF_GPIO_1_FALLING = 1,
    MHAL_GPIOIF_GPIO_1_BOTH_RISING_FALLING = 2,
    MHAL_GPIOIF_GPIO_1_RISING_RESERVED = 3,
    MHAL_GPIOIF_GPIO_1_EDGE_TYPE_MAX
} mhal_gpioif_gpio_1_edge_type;

typedef struct {
    u8 control_setting;
    u8 updown;
    u32 reset_value;
    u32 low_limit;
    u32 high_limit;
    u32 edge_type_gpio_0;
    u32 edge_type_gpio_1;
} mhal_gpioif_event_capture_setting;

struct mtk_gpioif_config {
    mhal_gpioif_source_clock clk;
    mhal_gpioif_group group;
    mhal_gpioif_event_counter_mode event_cnt_mode;
    mhal_gpioif_mode mode;
    mhal_gpioif_sa_mode_limit_select sa_mode_lim;
    mhal_gpioif_interrupt_limit_select inter_lim;
    mhal_gpioif_gpio_0_edge_type gpio_0_edge_type;
    mhal_gpioif_gpio_1_edge_type gpio_1_edge_type;
    mhal_gpioif_event_capture_setting *setting;
};

struct mtk_gpioif_int_count {
    u32 int_bit;
    u32 int_event_low_count;
    u32 int_event_high_count;
    u32 int_gpio2_rst_done_count;
    u32 int_event_over_count;
    u32 int_event_uf_count;
    u32 int_cap_f0_full_count;
    u32 int_cap_f1_full_count;
    u32 int_reset_cap_f0_full_count;
    u32 int_reset_cap_f1_full_count;
    u32 int_cap_f0_np_count;
    u32 int_cap_f1_np_count;
    u32 int_cap_f0_p_count;
    u32 int_cap_f1_p_count;
    u32 cap_fifo0[MAX_FIFO_ENTRY_CNT];
    u32 cap_fifo1[MAX_FIFO_ENTRY_CNT];
    u32 cap_fifo0_count;
    u32 cap_fifo1_count;
};


struct mtk_gpioif_controller {
    void __iomem *base[MHAL_GPIOIF_GROUP_MAX];
    void __iomem    *reg_clk_base;
    int  irq[MHAL_GPIOIF_GROUP_MAX];
    struct mtk_gpioif_config *mconfig;
    struct mtk_gpioif_int_count *int_cnt;
};

#ifdef __cplusplus
extern "C" {
#endif


int mtk_mhal_gpioif_select_clock_source(struct mtk_gpioif_controller *ctlr);

int mtk_mhal_gpioif_event_counter_setting(struct mtk_gpioif_controller *ctlr);

int mtk_mhal_gpioif_capture_counter_setting(struct mtk_gpioif_controller *ctlr);

int mtk_mhal_gpioif_enable_event_counter(struct mtk_gpioif_controller *ctlr);

int mtk_mhal_gpioif_disable_event_counter(struct mtk_gpioif_controller *ctlr);

int mtk_mhal_gpioif_enable_capture_counter(struct mtk_gpioif_controller *ctlr);

int mtk_mhal_gpioif_disable_capture_counter(struct mtk_gpioif_controller *ctlr);


int mtk_mhal_gpioif_software_reset(struct mtk_gpioif_controller *ctlr);

int mtk_mhal_gpioif_interrupt_bit_wise(
    struct mtk_gpioif_controller *ctlr, u32 bit, u8 enable);

int mtk_mhal_gpioif_hardware_reset_by_gpio_2(
    struct mtk_gpioif_controller *ctlr, int active_reset);

int mtk_mhal_gpioif_read_gpio_event_count(
    struct mtk_gpioif_controller *ctlr, unsigned int *pvalue);

int mtk_mhal_gpioif_read_gpio_cap_fifo0_value(
    struct mtk_gpioif_controller *ctlr, unsigned int *pvalue);

int mtk_mhal_gpioif_read_gpio_cap_fifo1_value(
    struct mtk_gpioif_controller *ctlr, unsigned int *pvalue);

int mtk_mhal_gpioif_de_glitch(
    struct mtk_gpioif_controller *ctlr, int gpio, int enable,
    unsigned int min_p, unsigned int init_v);

int mtk_mhal_gpioif_limit_comparator(struct mtk_gpioif_controller *ctlr);

int mtk_mhal_gpioif_global_reset(struct mtk_gpioif_controller *ctlr);

int mtk_mhal_gpioif_counter_clock_setting(
    struct mtk_gpioif_controller *ctlr, int enable);

int mtk_mhal_gpioif_isr_handle(struct mtk_gpioif_controller *ctlr);

int mtk_mhal_gpioif_read_reset_val(
    struct mtk_gpioif_controller *ctlr, unsigned int *pvalue);

int mtk_mhal_gpioif_read_low_limit_val(
    struct mtk_gpioif_controller *ctlr, unsigned int *pvalue);

int mtk_mhal_gpioif_read_high_limit_val(
    struct mtk_gpioif_controller *ctlr, unsigned int *pvalue);

#ifdef __cplusplus
}
#endif

#endif