mhal_pwm.h

/*
 * (C) 2005-2020 MediaTek Inc. All rights reserved.
 *
 * Copyright Statement:
 *
 * This MT3620 driver software/firmware and related documentation
 * ("MediaTek Software") are protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. ("MediaTek"). You may only use, reproduce, modify, or
 * distribute (as applicable) MediaTek Software if you have agreed to and been
 * bound by this Statement and the applicable license agreement with MediaTek
 * ("License Agreement") and been granted explicit permission to do so within
 * the License Agreement ("Permitted User"). If you are not a Permitted User,
 * please cease any access or use of MediaTek Software immediately.
 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
 * PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS
 * ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
 * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
 * INCORPORATED IN, OR SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO
 * LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
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 * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
 * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
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 * HEREUNDER WILL BE ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
 * RECEIVER TO MEDIATEK DURING THE PRECEDING TWELVE (12) MONTHS FOR SUCH
 * MEDIATEK SOFTWARE AT ISSUE.
 */

#ifndef __MHAL_PWM_H__
#define __MHAL_PWM_H__

#include "mhal_osai.h"

#define PWM_EPTR        1

#define PWM_EPARAMETER  2

#define PWM_ENOMEM      3

#define PWM_EFAULT      4

#define PWM_EAGAIN      5

#define PWM_ETIMEOUT    6

#define PWM_ECLK    7

#define MAX_GROUP_NUM 3

typedef enum {
    PWM_BIT0  = 0,
    PWM_BIT1  = 1,
    PWM_BIT2  = 2,
    PWM_BIT3  = 3,
    PWM_BITMAX
}   pwm_channels_bit_map;

typedef enum {
    PWM_IDLE = 0,
    PWM_BUSY = 1
}   pwm_running_status;

typedef enum  {
    PWM_DP0 = 0,
    PWM_DP1,
    PWM_DP2,
    PWM_DP3,
    PWM_DP_NUM
} pwm_differential_select;

typedef enum {
    PWM_CHANNEL0  = 0,
    PWM_CHANNEL1  = 1,
    PWM_CHANNEL2  = 2,
    PWM_CHANNEL3  = 3,
    PWM_CHANNEL_MAX
}   pwm_channels;

typedef enum {
    PWM_CLOCK_32K = 0,
    PWM_CLOCK_2M,
    PWM_CLOCK_XTAL,
    PWM_CLOCK_NUM
} pwm_clks;

typedef enum{
    PWM_STAGE_S0 = 0,
    PWM_STAGE_S1,
    PWM_STAGE_MAX
} pwm_s0_s1_stages;

struct mtk_com_pwm_data {
    const void __iomem *pwm_register;
    u32 pwm_nums;
    u32 index;
    pwm_differential_select  mode;
    u32  s0_stay_cycle;
    u32  s1_stay_cycle;
    u8  replay_mode;
    pwm_s0_s1_stages stage;
    u32  duty_cycle;
    u32  frequency;
    u32  total_count;
    u32  current_duty_cycle;
    u32  current_frequency;
    u8  global_kick_enable;
    u8  io_ctrl_sel;
    u8  polarity_set;
    pwm_running_status running_status;
};

struct mtk_pwm_controller {
    void __iomem *base;
    char group_number;
    pwm_clks group_clock;
    struct mtk_com_pwm_data *data;
};
#ifdef __cplusplus
extern "C" {
#endif

int mtk_mhal_pwm_clock_select(struct mtk_pwm_controller *ctlr);

int mtk_mhal_pwm_enable_clk(struct mtk_pwm_controller *ctlr,
        pwm_channels channel_num);

int mtk_mhal_pwm_disable_clk(struct mtk_pwm_controller *ctlr,
        pwm_channels channel_num);

int mtk_mhal_pwm_init(struct mtk_pwm_controller *ctlr,
    u32 channel_bit_map);

int mtk_mhal_pwm_deinit(struct mtk_pwm_controller *ctlr,
        u32 channel_bit_map);

int mtk_mhal_pwm_set_frequency(struct mtk_pwm_controller *ctlr,
        pwm_channels channel_num);

int mtk_mhal_pwm_set_duty_cycle(struct mtk_pwm_controller *ctlr,
        pwm_channels channel_num);

int mtk_mhal_pwm_start(struct mtk_pwm_controller *ctlr,
        pwm_channels channel_num);

int mtk_mhal_pwm_stop(struct mtk_pwm_controller *ctlr,
        pwm_channels channel_num);

int mtk_mhal_pwm_get_frequency(struct mtk_pwm_controller *ctlr,
        pwm_channels channel_num);

int mtk_mhal_pwm_get_duty_cycle(struct mtk_pwm_controller *ctlr,
    pwm_channels channel_num);

int mtk_mhal_pwm_get_running_status(struct mtk_pwm_controller *ctlr,
    pwm_channels channel_num);

int mtk_mhal_pwm_feature_enable(struct mtk_pwm_controller *ctlr,
        pwm_channels channel_num);

int mtk_mhal_pwm_config_s0_s1_freq_duty(struct mtk_pwm_controller *ctlr,
        pwm_channels channel_num);

int mtk_mhal_pwm_s0_s1_stay_cycle_config(struct mtk_pwm_controller *ctlr,
        pwm_channels channel_num);

int mtk_mhal_pwm_kick(struct mtk_pwm_controller *ctlr,
        pwm_channels channel_num);
int mtk_mhal_pwm_global_kick(struct mtk_pwm_controller *ctlr);
int mtk_mhal_pwm_dpsel(struct mtk_pwm_controller *ctlr,
        pwm_channels channel_num);

#ifdef __cplusplus
}
#endif

#endif /* __MHAL_PWM_H__ */