mhal_spim.h

/*
 * (C) 2005-2020 MediaTek Inc. All rights reserved.
 *
 * Copyright Statement:
 *
 * This MT3620 driver software/firmware and related documentation
 * ("MediaTek Software") are protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. ("MediaTek"). You may only use, reproduce, modify, or
 * distribute (as applicable) MediaTek Software if you have agreed to and been
 * bound by this Statement and the applicable license agreement with MediaTek
 * ("License Agreement") and been granted explicit permission to do so within
 * the License Agreement ("Permitted User"). If you are not a Permitted User,
 * please cease any access or use of MediaTek Software immediately.
 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
 * PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS
 * ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
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 * MEDIATEK SOFTWARE AT ISSUE.
 */

#ifndef __MHAL_SPI_MASTER__H__
#define __MHAL_SPI_MASTER__H__

#include "mhal_osai.h"

#define SPIM_EPTR       1

#define SPIM_ELENGTH        2

#define SPIM_ENOMEM     3

#define SPIM_EBUSY      4

#define MTK_SPIM_DMA_BUFFER_BYTES   (48 + 4)

enum spi_cpol {
    SPI_CPOL_0 = 0,
    SPI_CPOL_1 = 1
};

enum spi_cpha {
    SPI_CPHA_0 = 0,
    SPI_CPHA_1 = 1
};

enum spi_mlsb {
    SPI_LSB = 0,
    SPI_MSB = 1
};

enum spi_slave_sel {
    SPI_SELECT_DEVICE_0 = 0,
    SPI_SELECT_DEVICE_1 = 1,
};

enum spi_cs_polarity {
    SPI_CS_POLARITY_LOW = 0,
    SPI_CS_POLARITY_HIGH = 1,
};

typedef int (*spi_dma_done_callback) (void *user_data);

struct mtk_spi_config {
    enum spi_cpol cpol;
    enum spi_cpha cpha;
    enum spi_mlsb tx_mlsb;
    enum spi_mlsb rx_mlsb;
    enum spi_slave_sel slave_sel;
    enum spi_cs_polarity cs_polar;
};

struct mtk_spi_transfer {
    const void *tx_buf;
    void *rx_buf;
    u32 len;

    u32 opcode;

    u32 opcode_len;

    u32 use_dma;

    u32 speed_khz;
};

struct mtk_spi_private {
    u8 *tx_buf;

    dma_addr_t tx_dma;
    dma_addr_t rx_dma;

    u32 xfer_len;

    void *user_data;
    spi_dma_done_callback dma_done_callback;
};

struct mtk_spi_controller {
    void __iomem *base;
    void __iomem *cg_base;

    u8 *dma_tmp_tx_buf;

    int dma_tx_chan;
    int dma_rx_chan;

    struct mtk_spi_transfer *current_xfer;

    struct mtk_spi_private *mdata;
};

#ifdef __cplusplus
extern "C" {
#endif

int mtk_mhal_spim_dump_reg(struct mtk_spi_controller *ctlr);

int mtk_mhal_spim_clear_irq_status(struct mtk_spi_controller *ctlr);

int mtk_mhal_spim_fifo_handle_rx(struct mtk_spi_controller *ctlr,
                  struct mtk_spi_transfer *xfer);

int mtk_mhal_spim_prepare_hw(struct mtk_spi_controller *ctlr,
                  struct mtk_spi_config *config);

int mtk_mhal_spim_prepare_transfer(struct mtk_spi_controller *ctlr,
                    struct mtk_spi_transfer *xfer);

int mtk_mhal_spim_fifo_transfer_one(struct mtk_spi_controller *ctlr,
                    struct mtk_spi_transfer *xfer);


int mtk_mhal_spim_dma_done_callback_register(struct mtk_spi_controller *ctlr,
                         spi_dma_done_callback callback,
                         void *user_data);

int mtk_mhal_spim_dma_transfer_one(struct mtk_spi_controller *ctlr,
                   struct mtk_spi_transfer *xfer);

int mtk_mhal_spim_allocate_dma_chan(struct mtk_spi_controller *ctlr);

int mtk_mhal_spim_release_dma_chan(struct mtk_spi_controller *ctlr);

int mtk_mhal_spim_enable_clk(struct mtk_spi_controller *ctlr);

int mtk_mhal_spim_disable_clk(struct mtk_spi_controller *ctlr);

#ifdef __cplusplus
}
#endif

#endif