mhal_spis.h

/*
 * (C) 2005-2020 MediaTek Inc. All rights reserved.
 *
 * Copyright Statement:
 *
 * This MT3620 driver software/firmware and related documentation
 * ("MediaTek Software") are protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. ("MediaTek"). You may only use, reproduce, modify, or
 * distribute (as applicable) MediaTek Software if you have agreed to and been
 * bound by this Statement and the applicable license agreement with MediaTek
 * ("License Agreement") and been granted explicit permission to do so within
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 * please cease any access or use of MediaTek Software immediately.
 *
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 * THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
 * PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS
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 */

#ifndef __MHAL_SPI_SLAVE__H__
#define __MHAL_SPI_SLAVE__H__

#include "mhal_osai.h"

#define SET_TRANSFER_H2DMB(x, y, z) \
    ((0x1 << 6) | (x << 5) | (y << 4) | ((z) & 0xf))

#define SPIS_EPTR       1

#define SPIS_ELENGTH        2

#define SPIS_EMEM       3

#define SPIS_EBUSY      4

#define SPIS_EDMA       5

#define SPIS_EH2DMB     6

enum spis_cpol {
    SPIS_CPOL_0 = 0,
    SPIS_CPOL_1 = 1
};

enum spis_cpha {
    SPIS_CPHA_0 = 0,
    SPIS_CPHA_1 = 1
};

enum spis_opcode {
    OPCODE_SPIM_WRITE_SPIS_RX = 0x1,
    OPCODE_SPIM_READ_SPIS_TX = 0x2,
    OPCODE_SPIM_GET_SPIS_STATUS = 0x3,
    OPCODE_SPIM_SET_SPIS_IRQ = 0x8,
    OPCODE_SPIM_CLEAR_SPIS_D2HMB = 0x9,
    OPCODE_SPIM_SEND_SPIS_H2DMB = 0xa,
};

enum spis_tx_rx_flag {
    SPIM_READ_DATA_FROM_SPIS = 0x0,
    SPIM_WRITE_DATA_TO_SPIS = 0x1,
    SPIM_READ_STATUS_FROM_SPIS = 0x2,
    SPIM_WRITE_IRQ_MB_TO_SPIS = 0x3,
};

enum spis_d2hmb_state {
    SPIS_IDLE = 0x0,
    SPIS_READY = 0x1,
    SPIS_DONE = 0x2,
    SPIS_ERR = 0x4,
};

enum spis_direction_cmd {
    SPIM_READ_DATA = 0,
    SPIM_WRITE_DATA = 1,
};

typedef int (*spis_dma_done_callback) (void *user_data);


struct mtk_spis_config {
    enum spis_cpol cpol;
    enum spis_cpha cpha;
};

struct mtk_spis_transfer {
    void *tx_buf;
    void *rx_buf;
    unsigned int len;
    int direction;
    int use_dma;
};

struct mtk_spis_private {
    enum spis_d2hmb_state d2hmb_state;
    dma_addr_t tx_dma;
    dma_addr_t rx_dma;
    void *user_data;
    spis_dma_done_callback dma_done_callback;
};

struct mtk_spis_controller {
    void __iomem *base;
    void __iomem *cg_base;
    int dma_tx_chan;
    int dma_rx_chan;
    void *spis_tx_buf;
    void *spis_rx_buf;
    struct mtk_spis_transfer *xfer;
    struct mtk_spis_private *mdata;
};

#ifdef __cplusplus
extern "C" {
#endif

int mtk_mhal_spis_dump_reg(struct mtk_spis_controller *ctlr);

int mtk_mhal_spis_get_irq_status(struct mtk_spis_controller *ctlr);


int mtk_mhal_spis_clear_irq_status(struct mtk_spis_controller *ctlr);

int mtk_mhal_spis_handle_h2dmb(struct mtk_spis_controller *ctlr);

int mtk_mhal_spis_send_d2hmb(struct mtk_spis_controller *ctlr);

int mtk_mhal_spis_handle_rx(struct mtk_spis_controller *ctlr);

int mtk_mhal_spis_handle_tx(struct mtk_spis_controller *ctlr);


int mtk_mhal_spis_setup_hw(struct mtk_spis_controller *ctlr,
                  struct mtk_spis_config *config);

int mtk_mhal_spis_enable_irq(struct mtk_spis_controller *ctlr);

int mtk_mhal_spis_fifo_transfer_one(struct mtk_spis_controller *ctlr,
                    struct mtk_spis_transfer *xfer);


int mtk_mhal_spis_dma_done_callback_register(
                    struct mtk_spis_controller *ctlr,
                    spis_dma_done_callback callback);

int mtk_mhal_spis_dma_transfer_one(struct mtk_spis_controller *ctlr,
                   struct mtk_spis_transfer *xfer);


int mtk_mhal_spis_allocate_dma_chan(struct mtk_spis_controller *ctlr);

int mtk_mhal_spis_release_dma_chan(struct mtk_spis_controller *ctlr);

int mtk_mhal_spis_enable_clk(struct mtk_spis_controller *ctlr);

int mtk_mhal_spis_disable_clk(struct mtk_spis_controller *ctlr);

#ifdef __cplusplus
}
#endif


#endif