#define GET_SPIS_IRQ_TYPE(x) ((x >> 4) & 0x3)
static int spis_dma_chan[OS_HAL_SPIS_ISU_MAX][2] = {
};
#define ISU0_SPIS_BASE 0x38070400
#define ISU1_SPIS_BASE 0x38080400
#define ISU2_SPIS_BASE 0x38090400
#define ISU3_SPIS_BASE 0x380a0400
#define ISU4_SPIS_BASE 0x380b0400
static unsigned long spis_base_addr[OS_HAL_SPIS_ISU_MAX] = {
ISU0_SPIS_BASE,
ISU1_SPIS_BASE,
ISU2_SPIS_BASE,
ISU3_SPIS_BASE,
ISU4_SPIS_BASE,
};
#define ISU0_CG_BASE 0x38070000
#define ISU1_CG_BASE 0x38080000
#define ISU2_CG_BASE 0x38090000
#define ISU3_CG_BASE 0x380a0000
#define ISU4_CG_BASE 0x380b0000
static unsigned long cg_base_addr[OS_HAL_SPIS_ISU_MAX] = {
ISU0_CG_BASE,
ISU1_CG_BASE,
ISU2_CG_BASE,
ISU3_CG_BASE,
ISU4_CG_BASE,
};
spis_num bus_num)
{
if (bus_num > OS_HAL_SPIS_ISU_MAX - 1) {
printf("invalid, bus_num should be 0~%d\n",
OS_HAL_SPIS_ISU_MAX - 1);
return NULL;
}
return &g_spis_ctlr[bus_num];
}
void mtk_os_hal_spis_dump_reg(spis_num bus_num)
{
_mtk_os_hal_spis_get_ctlr(bus_num);
}
static int _mtk_os_hal_spis_irq_handler(spis_num bus_num)
{
int reg_val, ret = 0;
_mtk_os_hal_spis_get_ctlr(bus_num);
if (!ctlr)
return -1;
switch (GET_SPIS_IRQ_TYPE(reg_val)) {
if (ret)
break;
else
break;
break;
break;
printf("Read SPIS status\n");
break;
}
return ret;
}
static void _mtk_os_hal_spis0_irq_event(void)
{
_mtk_os_hal_spis_irq_handler(OS_HAL_SPIS_ISU0);
}
static void _mtk_os_hal_spis1_irq_event(void)
{
_mtk_os_hal_spis_irq_handler(OS_HAL_SPIS_ISU1);
}
static void _mtk_os_hal_spis2_irq_event(void)
{
_mtk_os_hal_spis_irq_handler(OS_HAL_SPIS_ISU2);
}
static void _mtk_os_hal_spis3_irq_event(void)
{
_mtk_os_hal_spis_irq_handler(OS_HAL_SPIS_ISU3);
}
static void _mtk_os_hal_spis4_irq_event(void)
{
_mtk_os_hal_spis_irq_handler(OS_HAL_SPIS_ISU4);
}
static void _mtk_os_hal_spis_request_irq(int bus_num)
{
switch (bus_num) {
case 0:
CM4_Install_NVIC(CM4_IRQ_ISU_G0_SPIS, DEFAULT_PRI,
IRQ_LEVEL_TRIGGER, _mtk_os_hal_spis0_irq_event,
TRUE);
break;
case 1:
CM4_Install_NVIC(CM4_IRQ_ISU_G1_SPIS, DEFAULT_PRI,
IRQ_LEVEL_TRIGGER, _mtk_os_hal_spis1_irq_event,
TRUE);
break;
case 2:
CM4_Install_NVIC(CM4_IRQ_ISU_G2_SPIS, DEFAULT_PRI,
IRQ_LEVEL_TRIGGER, _mtk_os_hal_spis2_irq_event,
TRUE);
break;
case 3:
CM4_Install_NVIC(CM4_IRQ_ISU_G3_SPIS, DEFAULT_PRI,
IRQ_LEVEL_TRIGGER, _mtk_os_hal_spis3_irq_event,
TRUE);
break;
case 4:
CM4_Install_NVIC(CM4_IRQ_ISU_G4_SPIS, DEFAULT_PRI,
IRQ_LEVEL_TRIGGER, _mtk_os_hal_spis4_irq_event,
TRUE);
break;
}
}
static void _mtk_os_hal_spis_free_irq(int bus_num)
{
switch (bus_num) {
case 0:
NVIC_DisableIRQ(CM4_IRQ_ISU_G0_SPIS);
break;
case 1:
NVIC_DisableIRQ(CM4_IRQ_ISU_G1_SPIS);
break;
case 2:
NVIC_DisableIRQ(CM4_IRQ_ISU_G2_SPIS);
break;
case 3:
NVIC_DisableIRQ(CM4_IRQ_ISU_G3_SPIS);
break;
case 4:
NVIC_DisableIRQ(CM4_IRQ_ISU_G4_SPIS);
break;
}
}
static int _mtk_os_hal_spis_dma_done_callback(void *data)
{
printf("in spis dma callback, len(%d)\n",
}
return 0;
}
int mtk_os_hal_spis_ctlr_init(spis_num bus_num)
{
_mtk_os_hal_spis_get_ctlr(bus_num);
if (!ctlr)
return -1;
ctlr->
base = (
void __iomem *)spis_base_addr[bus_num];
ctlr->
cg_base = (
void __iomem *)cg_base_addr[bus_num];
ctlr->
mdata = &g_spis_mdata[bus_num];
ctlr->
xfer = &g_spis_xfer[bus_num];
_mtk_os_hal_spis_dma_done_callback);
_mtk_os_hal_spis_request_irq(bus_num);
return 0;
}
int mtk_os_hal_spis_ctlr_deinit(spis_num bus_num)
{
_mtk_os_hal_spis_get_ctlr(bus_num);
if (!ctlr)
return -1;
_mtk_os_hal_spis_free_irq(bus_num);
return 0;
}
int mtk_os_hal_spis_setup_hw(spis_num bus_num,
{
_mtk_os_hal_spis_get_ctlr(bus_num);
if (!ctlr)
return -1;
return 0;
}
int mtk_os_hal_spis_register_buffer(spis_num bus_num,
{
_mtk_os_hal_spis_get_ctlr(bus_num);
if (!ctlr) {
printf("%s fail", __func__);
return -1;
}
if (!spis_tx_buf && !spis_rx_buf) {
printf("%s SPIS Tx/Rx buffer is NULL", __func__);
return -1;
}
return 0;
}