mhal_adc.h

/*
 * (C) 2005-2020 MediaTek Inc. All rights reserved.
 *
 * Copyright Statement:
 *
 * This MT3620 driver software/firmware and related documentation
 * ("MediaTek Software") are protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. ("MediaTek"). You may only use, reproduce, modify, or
 * distribute (as applicable) MediaTek Software if you have agreed to and been
 * bound by this Statement and the applicable license agreement with MediaTek
 * ("License Agreement") and been granted explicit permission to do so within
 * the License Agreement ("Permitted User"). If you are not a Permitted User,
 * please cease any access or use of MediaTek Software immediately.
 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
 * PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS
 * ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
 * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
 * INCORPORATED IN, OR SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO
 * LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
 * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
 * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
 * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
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 * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED
 * HEREUNDER WILL BE ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
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 * MEDIATEK SOFTWARE AT ISSUE.
 */


#ifndef __MHAL_ADC_H__
#define __MHAL_ADC_H__

#include "mhal_osai.h"

#define ADC_EPTR        1

#define ADC_EPARAMETER  2

#define ADC_ENOMEM      3

#define ADC_EFAULT      4

#define ADC_EAGAIN      5

/***************************************************************************
   * enums
   **************************************************************************/
typedef enum {
    ADC_PMODE_ONE_TIME = 0,
    ADC_PMODE_PERIODIC
} adc_pmode;

typedef enum {
    ADC_AVG_1_SAMPLE = 0,
    ADC_AVG_2_SAMPLE,
    ADC_AVG_4_SAMPLE,
    ADC_AVG_8_SAMPLE,
    ADC_AVG_16_SAMPLE,
    ADC_AVG_32_SAMPLE,
    ADC_AVG_64_SAMPLE
} adc_avg_mode;

typedef enum {
    ADC_FIFO_DIRECT = 0,
    ADC_FIFO_DMA
} adc_fifo_mode;

typedef enum {
    ADC_FIFO_IER_BOTH = 0,
    ADC_FIFO_IER_RXFULL,
    ADC_FIFO_IER_TIMEOUT
} adc_fifo_ier_mode;

typedef enum {
    ADC_BIT0 = 0x0001,
    ADC_BIT1 = 0x0002,
    ADC_BIT2 = 0x0004,
    ADC_BIT3 = 0x0008,
    ADC_BIT4 = 0x0010,
    ADC_BIT5 = 0x0020,
    ADC_BIT6 = 0x0040,
    ADC_BIT7 = 0x0080,
} adc_channel_bit_map;

typedef enum {
    ADC_CHANNEL_0 = 0,
    ADC_CHANNEL_1 = 1,
    ADC_CHANNEL_2 = 2,
    ADC_CHANNEL_3 = 3,
    ADC_CHANNEL_4 = 4,
    ADC_CHANNEL_5 = 5,
    ADC_CHANNEL_6 = 6,
    ADC_CHANNEL_7 = 7,
    ADC_CHANNEL_MAX
} adc_channel;

typedef void (*adc_dma_callback_func) (void *user_data);

struct adc_fsm_param {
    adc_pmode   pmode;
    u16 channel_map;
    u32 sample_rate;
    adc_fifo_mode fifo_mode;
    u32 *vfifo_addr;
    u32 vfifo_len;
    u32 rx_period_len;
    adc_fifo_ier_mode ier_mode;
    adc_dma_callback_func rx_callback_func;
    void *rx_callback_data;
};

struct mtk_adc_controller {
    void __iomem *base;
    void __iomem *cg_base;
    struct adc_fsm_param *adc_fsm_parameter;
    u16 adc_processing;
    dma_addr_t  rx_addr;
    u8 dma_channel;
};

#ifdef __cplusplus
extern "C" {
#endif

int mtk_mhal_adc_init(struct mtk_adc_controller *ctlr);

int mtk_mhal_adc_deinit(struct mtk_adc_controller *ctlr);
int mtk_mhal_adc_fsm_param_set(struct mtk_adc_controller *ctlr,
        struct adc_fsm_param *adc_fsm_parameter);

int mtk_mhal_adc_start(struct mtk_adc_controller *ctlr);

int mtk_mhal_adc_stop(struct mtk_adc_controller *ctlr);

int mtk_mhal_adc_enable_clk(struct mtk_adc_controller *ctlr);

int mtk_mhal_adc_disable_clk(struct mtk_adc_controller *ctlr);
int mtk_mhal_adc_fifo_handle_rx(struct mtk_adc_controller *ctlr);

#ifdef __cplusplus
}
#endif

#endif /* __MHAL_ADC_H__ */