This structure defines ADC related parameters,
such as ADC mode, sample times, channel map, and interrupt mode. More...

#include <mhal_adc.h>

Data Fields
adc_pmode	pmode
	ADC mode, one shot or periodic mode. More...

u16	channel_map
	ADC bit map, REG_CH_MAP[7:0]=8'0000_0011, enable CH0 & CH1.

u32	sample_rate
	Sample rate used in periodic mode, for example, the sampling rate can be set as 10K, ch_num * sample_rate <= 90K. More...

adc_fifo_mode	fifo_mode
	ADC operation mode: FIFO or DMA mode, one shot mode use ADC_FIFO_DIRECT, periodic mode use ADC_FIFO_DMA.

u32 *	vfifo_addr
	ADC Virtual FIFO address for periodic or one shot mode, record the data storage the SRAM address passed by user, HW will put sampling data to this buffer. More...

u32	vfifo_len
	ADC Virtual FIFO length. More...

u32	rx_period_len
	ADC rx period length. More...

adc_fifo_ier_mode	ier_mode
	ADC interrupt mode, config ADC_FIFO_IER_RXFULL irq enable.

adc_dma_callback_func	rx_callback_func
	RX DMA callback function.

void *	rx_callback_data
	RX DMA callback data.

Detailed Description

This structure defines ADC related parameters,
such as ADC mode, sample times, channel map, and interrupt mode.

Field Documentation

adc_pmode pmode

ADC mode, one shot or periodic mode.

u32 sample_rate

Sample rate used in periodic mode, for example, the sampling
rate can be set as 10K, ch_num * sample_rate <= 90K.

Please note due to the sample_rate calculation formula, there
might be some deviation. The following is the exact value:
Configuration Value : Real Sampling Rate (when 1 channel)
48000 : 48.78KHz
44100 : 44.44KHz
32000 : 32.26KHz
24000 : 24.10KHz
22050 : 22.22KHz
16000 : 16.00KHz
12000 : 12.05KHz
11025 : 11.05KHz
10000 : 10.00KHz
8000 : 8.00KHz
1000 : 1.00KHz
100 : 0.10KHz
10 : 0.01KHz
1 : 0.001KHz
The calculation formula of sample_rate(TS) is as follows:
TS = ADC_CLOCK/{(REG_T_INIT + 1) + [((REG_T_CH + 2) +
(avg_num + 1))] * ch_num + (REG_PERIOD + 1)}
ADC_CLOCK select 2M, ADC initial stable time(REG_T_INIT) set as 20,
channel stable time(REG_T_CH) set as 8, sample average number(avg_num)
can select be set to 1, 2, 4, 8, 16, 32, 64. (REG_PERIOD)ADC clock
cycle count period, unit as clock cycle, max value 0xFFFFFFFF,
1 < ch_num < 8.

u32* vfifo_addr

ADC Virtual FIFO address for periodic or one shot mode,
record the data storage the SRAM address passed by user, HW will
put sampling data to this buffer.

Each sampling data takes 4 bytes, bit[3:0] is the channel
number information, bit[15:4] is the sample raw data, user can use
the following formula to convert raw data to voltage:
voltage = raw data * 2500 / 4096, val bit[32:16] is debug info,
no need to care.

u32 vfifo_len

ADC Virtual FIFO length.

Periodic Mode: vfifo_len is the total number of the ADC sampling data
ex, vfifo_len=16 means the buffer could store totally 16 ADC sampling data (16x4=64 Bytes)
ex, vfifo_len=1024 means the buffer could store totally 1024 ADC sampling data (1024x4=4096 Bytes)
One Shot Mode: vfifo_len is the number of enabled channels

u32 rx_period_len

ADC rx period length.

Periodic Mode: rx_period_len is the duration for ADC driver to invoke RTApp callback function.
ex, rx_period_len=4 means the callback function is invoked whenever 4 sampling data captured.
ex, rx_period_len=256 means the callback function is invoked whenever 256 sampling data captured.
One Shot Mode: rx_period_len is the number of enabled channels.

The documentation for this struct was generated from the following file:

mhal_adc.h

Data Fields

Detailed Description

Field Documentation