os_hal_dma.h

/*
 * (C) 2005-2020 MediaTek Inc. All rights reserved.
 *
 * Copyright Statement:
 *
 * This MT3620 driver software/firmware and related documentation
 * ("MediaTek Software") are protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. ("MediaTek"). You may only use, reproduce, modify, or
 * distribute (as applicable) MediaTek Software if you have agreed to and been
 * bound by this Statement and the applicable license agreement with MediaTek
 * ("License Agreement") and been granted explicit permission to do so within
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 * please cease any access or use of MediaTek Software immediately.
 *
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 * THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
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 */

#ifndef __OS_HAL_DMA_H__
#define __OS_HAL_DMA_H__

#include "mhal_dma.h"

enum dma_channel {
    DMA_ISU0_TX_CH0,
    DMA_ISU0_RX_CH1,
    DMA_ISU1_TX_CH2,
    DMA_ISU1_RX_CH3,
    DMA_ISU2_TX_CH4,
    DMA_ISU2_RX_CH5,
    DMA_ISU3_TX_CH6,
    DMA_ISU3_RX_CH7,
    DMA_ISU4_TX_CH8,
    DMA_ISU4_RX_CH9,
    DMA_M2M_CH12 = 12,
    VDMA_ISU0_TX_CH13,
    VDMA_ISU0_RX_CH14,
    VDMA_ISU1_TX_CH15,
    VDMA_ISU1_RX_CH16,
    VDMA_ISU2_TX_CH17,
    VDMA_ISU2_RX_CH18,
    VDMA_ISU3_TX_CH19,
    VDMA_ISU3_RX_CH20,
    VDMA_ISU4_TX_CH21,
    VDMA_ISU4_RX_CH22,
    VDMA_I2S0_TX_CH25 = 25,
    VDMA_I2S0_RX_CH26,
    VDMA_I2S1_TX_CH27,
    VDMA_I2S1_RX_CH28,
    VDMA_ADC_RX_CH29,
};

enum dma_param_type {
    OS_HAL_DMA_PARAM_RLCT = 0,
    OS_HAL_DMA_PARAM_FIX_ADDR = 1,
    OS_HAL_DMA_PARAM_PROG_ADDR = 2,
    OS_HAL_DMA_PARAM_VFF_FIFO_SIZE = 3,
    OS_HAL_DMA_PARAM_VFF_FIFO_CNT = 4,
    OS_HAL_DMA_PARAM_VFF_HWPTR = 5,
    OS_HAL_DMA_PARAM_VFF_SWPTR = 6,
};

enum dma_interrupt_type {
    DMA_INT_COMPLETION = 0x1 << 0,
    DMA_INT_HALF_COMPLETION = 0x1 << 1,
    DMA_INT_VFIFO_TIMEOUT = 0x1 << 2,
    DMA_INT_VFIFO_THRESHOLD = 0x1 << 3,
};
typedef void (*dma_interrupt_callback)(void *user_data);
struct dma_wrap {
    u8 wrap_en;
    u8 wrap_side;
    u32 wrap_point;
    u32 wrap_to_addr;
};

struct dma_control_mode {
    u8 burst_type;
    u8 bw_transfer_en;
    u8 dst_inc_en;
    u8 src_inc_en;
    u8 transize;
    u8 bw_limiter;
    struct dma_wrap wrap_settings;
};

struct dma_interrupt {
    dma_interrupt_callback isr_cb;
    void *cb_data;
};

struct dma_vfifo {
    u32 fifo_thrsh;
    u8 alert_cmp_type;
    u32 alert_len;
    u32 fifo_size;
    u32 timeout_cnt;
};

struct dma_setting {
    u8 interrupt_flag;
    u8 dir;
    u32 src_addr;
    u32 dst_addr;
    u32 count;
    u8 reload_en;
    struct dma_vfifo vfifo;
    struct dma_control_mode ctrl_mode;
};
#ifdef __cplusplus
extern "C" {
#endif

int mtk_os_hal_dma_alloc_chan(enum dma_channel chn);

int mtk_os_hal_dma_config(enum dma_channel chn, struct dma_setting *setting);

int mtk_os_hal_dma_start(enum dma_channel chn);

int mtk_os_hal_dma_stop(enum dma_channel chn);

int mtk_os_hal_dma_pause(enum dma_channel chn);

int mtk_os_hal_dma_resume(enum dma_channel chn);

int mtk_os_hal_dma_get_status(enum dma_channel chn);

int mtk_os_hal_dma_register_isr(enum dma_channel chn,
    dma_interrupt_callback callback, void *callback_data,
                enum dma_interrupt_type isr_type);

int mtk_os_hal_dma_dump_register(enum dma_channel chn);

int mtk_os_hal_dma_set_param(enum dma_channel chn,
    enum dma_param_type param_type, u32 value);

int mtk_os_hal_dma_get_param(enum dma_channel chn,
    enum dma_param_type param_type);

int mtk_os_hal_dma_update_swptr(enum dma_channel chn, u32 length_byte);

int mtk_os_hal_dma_vff_read_data(enum dma_channel chn, u8 *buffer, u32 length);

int mtk_os_hal_dma_release_chan(enum dma_channel chn);

int mtk_os_hal_dma_reset(enum dma_channel chn);

int mtk_os_hal_dma_clr_dreq(enum dma_channel chn);

#ifdef __cplusplus
}
#endif

#endif